Senior Wireless Software Engineer - MAC Layer - TeraWave

Company: Blue Origin

Location: Seattle, WA

Salary: $197,529.00 - $276,539.55 a year

Type: Full-time

Posted: 2026-04-23

About this role

Application close date:

Applications will be accepted on an ongoing basis until the requisition is closed.

At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflight!

As a Principal Software Engineer for Dataplane & Edge Infrastructure, you will serve as the primary architect and builder of the TeraWave Point of Presence (PoP) infrastructure. You will lead the design and implementation of next-generation PoP systems, writing the low-level software that handles terabits of traffic with surgical precision. This role requires deep expertise in high-performance networking, systems-level programming, and edge infrastructure to define TeraWave's competitive advantage in satellite communications. You will be responsible for building and optimizing the high-performance data path that processes packets at wire speed, while mentoring engineers and setting technical standards for code quality and system design across the team.

Responsibilities include but are not limited to:

  • Architect a scalable, resilient, and ultra-high-performance Point of Presence from the ground up, establishing foundational technical standards and design principles for TeraWave's PoP infrastructure
  • Build and optimize the dataplane using DPDK and VPP to ensure wire-speed packet processing and maximum network throughput
  • Implement and fine-tune IP networking stacks, including BGP, OSPF, and custom routing logic to support TeraWave's edge networking requirements
  • Drive performance engineering efforts to identify and eliminate bottlenecks at the software-hardware interface, optimizing for throughput, latency, and CPU cache efficiency
  • Provide technical leadership by mentoring senior engineers and establishing standards for code ...

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