AI - UVM Verification Engineer

About this role

Company Description
Paradigm Works, Inc. delivers world-class chip development services, software and training (Sunburst Design) for digital integrated circuits, with a strong focus on innovation, technical excellence, and customer service. The company is a pioneer in verification and design services, custom enabling IP, and training for chip development. Paradigm Works partners with clients across major global markets, supporting complex projects and advanced semiconductor designs. Its consulting expertise spans AI driven Architecture, Design, Synthesis, Functional Verification, Timing Closure, Test, and Physical Design, offering comprehensive end-to-end support for chip development teams.

Role Description
This is a full-time remote role for a UVM Verification Engineer. Using leading AI tools, the UVM Verification Engineer will develop and maintain SystemVerilog/UVM testbenches, including stimulus generation, checkers, monitors, and scoreboards to verify complex RTL designs. Responsibilities include creating test plans, writing and executing tests, debugging simulation failures, and collaborating closely with design, validation, and architecture teams to ensure functional correctness and coverage goals. The engineer will analyze verification results, track defects, refine test environments, and contribute to continuous improvement of verification methodologies and automation. The role may also involve mentoring other team members, reviewing verification collateral, and supporting client-facing technical discussions when needed.

Qualifications

• AI experience or interest in learning AI for verification.
• Strong RTL Design and Functional Verification skills, including experience with SystemVerilog and UVM.
• Proficiency in Debugging and Validation of complex digital designs using simulation and related tools.
• Understanding of Good Manufacturing Practice (GMP) or similar quality and process compliance frameworks, where applicable.
• Experience with E...